(a) Field of the Invention
The present invention relates to a data latch circuit having anti-fuse elements and, more particularly, to a data latch circuit having functions of programming anti-fuse elements with desired data and delivering the nonvolatile data stored in the anti-fuse elements.
(b) Description of the Related Art
In an LSI including a memory circuit, it is difficult to perfectly exclude defects in some of the memory cells during manufacturing the memory circuit. To remedy a product memory device including therein one or more defective memory cells, redundant memory cells are generally used in the memory device to replace the detective memory cells by the redundant memory cells.
The remedy information as to the remedy of the defective memory cells by the redundant memory cells is stored in nonvolatile memory elements, such as EPROM elements which are electrically programmable, fuse elements which are fused by a critical current to assume an electrically open state, and anti-fuse elements (or non-fuse elements) which are applied with a critical voltage to be short-circuited due to the dielectric breakdown thereof.
Among other nonvolatile memory elements for storing the remedy information, the anti-fuse elements are generally preferable especially in a mixed LSI including together a logic macro block and a large-capacity memory macro block, such as SRAM and DRAM. The anti-fuse elements are superior to the EPROM elements which require a large number of fabrication steps and thus the increased costs thereof. The anti-fuse elements are superior to the fuse elements which prohibit metallic interconnections from being disposed overlying the fuse elements in view of the heat generated in the fuse elements during the fusing operation thereof and thus require an increased occupied area.
The anti-fuse elements have an advantage in that the current passing through the anti-fuse elements during the dielectric breakdown thereof is considerably smaller than the current used for fusing the fuse elements, especially in the case of capacitive anti-fuse elements, and thus the heat generated by the dielectric breakdown can be neglected for the safe operation.
However, there is a problem in the conventional anti-fuse elements that the anti-fuse elements have an average resistance around several hundreds of ohms after the dielectric breakdown, wherein some anti-fuse elements may have several tens of kilo-ohms at the maximum, although this is a relatively rare case. In the case of several tens of kilo-ohms for the resistance of the anti-fuse elements, the judgement whether the anti-fuse elements are conductive or non-conductive is difficult and must be performed by using a detector having a higher sensitivity.
JP domestic publication 2000-503794 for PCT describes a data latch circuit including a detector having an improved sensitivity for the data stored in the anti-fuse elements. FIG. 11 shows the data latch circuit described in the publication, wherein anti-fuse elements to be detected for the resistances thereof are implemented as capacitive anti-fuse elements 77 and 78.
A power supply voltage is applied through terminal VDD to the sources of pMOSFETs 71 and 72, a programming voltage is applied through terminal VPRG to the sources of pMOSFETs 81 and 82, first and second bypass voltages PB are applied to the gates of pMOSFETs 73 and 74, respectively.
To program the capacitive anti-fuse elements 77 and 78 to a logic level xe2x80x9c1xe2x80x9d, capacitive anti-fuse element 77 is subjected to dielectric breakdown of the gate insulation film. More specifically, for the programming, nMOSFETs 75, 76, 79, 80 and 84 are turned OFF, pMOSFET 81 and nMOSFET 83v are turned ON, and pMOSFET 82 is turned OFF. Due to the potential difference, which is equal to the programming voltage, between both the plates (electrodes) of capacitive element 77, capacitive element 77 having a dielectric withstand voltage lower than the programming voltage is subjected to a dielectric breakdown, whereby the resistance of capacitive element 77 is reduced. On the other hand, since both the plates of capacitive element 78 have no potential difference therebetween, capacitive element 78 maintains a higher insulating resistance.
To read the data from the capacitive elements 77 and 78 in the data latch circuit, nMOSFETs 79 and 80 are turned ON, nMOSFETs 75 and 76 are applied with the bypass voltages PB, and pMOSFETs 81 and 82 and nMOSFETs 83 and 84 are turned OFF. The cross connection between the drain of each of pMOSFETs 71 and 72 and the gate of the other of pMOSFETs 71 and 72 allows a difference between the currents passing through the capacitive anti-fuse elements 77 and 78 to be amplified and delivered as an amplified difference signal from the detector. In this case, since the current passing through capacitive element 77 subjected to the dielectric breakdown is larger than the current passing through capacitive element 78 not subjected to dielectric breakdown, output terminal RCB assumes a low level whereas output terminal RC assumes a high level, thereby delivering a logic level xe2x80x9c1xe2x80x9d from the data latch circuit.
The conventional detector as described above can detect the stored data even from the capacitive anti-fuse element having a resistance as high as several tens of kilo-ohms after the dielectric breakdown. However, the above publication is silent to the concrete structure of the capacitive anti-fuse elements 77 and 78 except that the first-conductivity-type plate and second-conductivity-type plate are provided in the capacitive elements, and that the power supply voltage applied through terminals VDD is applied to these plates via nMOSFETs 75 and 76 effecting voltage drops.
It is considered from the description that each capacitive element has a thin dielectric film between the plates thereof, and that the thin dielectric film may be broken by direct application of the supply voltage. Since it is unclear whether or not the programming voltage is higher than the supply voltage, it is also unclear whether the pMOSFETs such as 81 and 82 applied with the programming voltage has a withstand voltage higher than the withstand voltage of pMOSFETs 71 and 72 applied with the supply voltage, or has a withstand voltage equal to the withstand voltage of pMOSFETs 71 and 72.
In short, although the above publication describes the structure of the detector for detecting the data stored in the data latch circuit, the publication does not show the concrete structures of the anti-fuse elements and the transistor elements constituting the programming circuit and thus the concrete structure of the data latch circuit as a whole.
In addition, the detector described in the publication has a large occupied area because of a large number (12) of MOSFETs including eight high-withstand-voltage MOSFETs 81, 82, 75, 76, 79, 80, 83 and 84 including gates having a larger thickness, assuming that the programming voltage is higher than the supply voltage.
In view of the above, it is an object of the present invention to provide a data latch circuit including anti-fuse elements, which is capable of being manufactured with a reduced number of transistor elements and thus with reduced costs and reduced occupied area.
The present invention provides a data latch circuit including: a voltage selection block for selecting one of a normal operating voltage supplied from a first power source and a programming voltage supplied from a second power source, to output a selected voltage through a voltage selection node; a first first-conductivity-type MOSFET including a source and a backgate connected together to the voltage selection node, a gate connected to a first output terminal, and a drain connected to a second output terminal; a second first-conductivity-type MOSFET including a source and a backgate connected together to the voltage selection node, a gate connected to the second output terminal, and a drain connected to the first output terminal; a first anti-fuse element including a first electrode connected to the first output terminal, a second electrode connected to a third power source, and an insulating film sandwiched between the first electrode and the second electrode and having a first withstand voltage lower than the programming voltage; a second anti-fuse element including a first electrode connected to the second output terminal, a second electrode connected to the third power source, and an insulating film sandwiched between the first electrode and the second electrode and having the first withstand voltage; a first second-conductivity-type MOSFET including a drain connected to the second output terminal, a gate for receiving a first control signal, and a source and a backgate connected together to the third power source; a second second-conductivity-type MOSFET including a drain connected to the first output terminal, a gate receiving a second control signal, and a source and backgate connected the third power source, wherein each of the first and second first-conductivity-type MOSFETs and the first and second second-conductivity-type MOSFETs includes a gate insulation film having a second withstand voltage higher than the programming voltage.
The present invention also provides a semiconductor device including: an internal logic circuit operating at a first voltage supplied from a first power source, the internal logic circuit including internal MOSFETs each having a gate insulation film having a first withstand voltage; an I/O circuit block operating at a second voltage higher than the first voltage and including I/O MOSFETs for inputting/outputting a signal for the internal logic circuit, at least one of the I/O MOSFETs including a gate insulation film having a second withstand voltage higher than the first withstand voltage; and a memory macro block including a remedy circuit, a plurality of ordinary memory mats and at least one redundant memory mat, each of the ordinary memory mats and the redundant memory mat including a memory cell array, a column selection section and a read/write section, the remedy circuit including a plurality of data latch circuits each for storing remedy information and having functions of inactivating the read/write section of a corresponding one of the ordinary memory mats and activating the read/write section of the redundant memory mat, each of the data latch circuits including: a voltage selection block for selecting one of the first voltage and the second voltage to output a selected voltage through a voltage selection node; a first first-conductivity-type MOSFET including a source and a backgate connected together to the voltage selection node, a gate connected to a first output terminal, and a drain connected to a second output terminal; a second first-conductivity-type MOSFET including a source and a backgate connected together to the voltage selection node, a gate connected to the second output terminal, and a drain connected to the first output terminal; a first anti-fuse element including a first electrode connected to the first output terminal, a second electrode connected to a third power source, and an insulating film sandwiched between the first electrode and the second electrode and having a first withstand voltage lower than the programming voltage; a second anti-fuse element including a first electrode connected to the second output terminal, a second electrode connected to the third power source, and an insulating film sandwiched between the first electrode and the second electrode and having the first withstand voltage; a first second-conductivity-type MOSFET including a drain connected to the second output terminal, a gate receiving a first control signal, and a source and a backgate connected together to the third power source; a second second-conductivity-type MOSFET including a drain connected to the first output terminal, a gate receiving a second control signal, and a source and backgate connected the third power source, wherein each of the first and second first-conductivity-type MOSFETs and the first and second second-conductivity-type MOSFETs includes a gate insulation film having a second withstand voltage higher than the programming voltage.
In accordance with the data latch circuit and the semiconductor device of the present invention, the data latch circuit including the anti-fuse elements has a higher sensitivity for detecting the programmed data, and can be manufactured with a reduced number of transistor elements, a reduced number of high-withstand-voltage MOSFETs and thus with a reduced occupied area. The anti-fuse elements and transistor elements constituting the data latch circuit may be fabricated by a common process for forming MOSFETs in an internal logic circuit and I/O circuit block.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.